Investment in the CAD EDA Industry

• The news that NXP might be pulling out of the Crolles2 alliance with ST Microelectronics and other partners brings up some interesting questions. Just how strong are these alliances and are they alliances of equals?
  
  
  The reasons behind the formation of various consortia in the semiconductor industry are fairly clear. In the early days of the semiconductor industry, the IDM (integrated device manufacturer) handled all the design and manufacturing. Most of the tools were developed in-house, as were the design and manufacturing processes. As the semiconductor industry matured, the evolution of the supply chain meant that various parts of the design to manufacturing workflow were disaggregated. The foundry model and the concurrent rise of the fabless semiconductor company represent this new supply chain for the semiconductor industry. The rise of the EDA companies was also part of this disaggregation.
  
  
  The continued advancement of Moore’s law has meant that process geometries have kept becoming smaller over the years, with new nodes appearing every 2-3 years of late. The SIA roadmap has helped define these nodes, and the various parts of the semiconductor supply chain have been able to maintain their contributions to the continued progress of the roadmap. However, with the last two nodes 65nm and 45nm, things have changed significantly from the previous historical trend, representing a discontinuity. The cost of building, equipping and maintaining new fabs has gone up tremendously. In the quest for smaller feature sizes, narrower line widths and different kinds of equipment to be able to etch these smaller features on the silicon substrate and still be able to get decent yields, the cost of research and development (R&D) for the tools and processes required to support this activity has gone up tremendously.
  
  
  Who pays for the R&D efforts required to sustain the move to smaller and smaller nodes? Who can afford to bear the huge costs? In GarySmithEDA’s opinion, this dilemma was the impetus for the creation of various industry alliances and consortia. The idea is to share the cost and risk for R&D across various stakeholders in the industry—the IDMs, fabless companies, foundries and semiconductor equipment manufacturers. Creating a pool of research that can be commercialized and productized throughout the supply chain will benefit all the stakeholders while also keeping on track with the roadmap predictions for process geometries and nodes.
  
  
  The result has been interesting. Several alliances/consortia have been formed. Some of these are fairly loose alliances whose members have a stake in other consortia, as well. In a sense, companies are diversifying their risk portfolio by making alliances with different partners simultaneously. However, at the end of the day, the question that remains unanswered is if these alliances are partnerships of equals or if some stakeholders are more equal than others.
  
  It used to be that the IDMs with captive fabs had the advantage of being able to test their proprietary tools and processes in internal fabs and commercialize the process manufacturing techniques for the next node about 18 to 24 months before the foundries could. With the emergence of industry alliances, though, the public message was that the delay between the process being implemented by the IDM and released to the foundry would come down to as little as 6 months.
  
  
  Has this really happened? GarySmithEDA wonders if these consortia are truly equitable alliances or if the IDMs are really at an advantage. The IDM’s profit/risk premium is rewarded first before the process hits the mainstream. This could impact the profit premium that independent foundries can charge in comparison with the IDMs as they are just behind the curve. With regard to the other partners in the consortia, such as semiconductor equipment manufacturers, equipment manufacturers have to make quite a bit of R & D investment in the new and emerging process technologies to support the new nodes. Anecdotal evidence suggests that the cost burden is going up tremendously for the equipment companies as well and they are looking to the consortia to spread the risks and costs. One of the risks that semiconductor equipment vendors face is the cancellation of equipment orders for new processes that they may invested in heavily. However, if they are co-invested in the technology and process development, the risk of cancellation may be lowered significantly so they can better manage their future revenue expectation.
  
  
  The other big factor to be considered is EDA tools. The EDA companies have been strong partners for the different stakeholders in the semiconductor industry through all of the process nodes. However, with so much at stake going forward as we hit 32 nm and below, will all of the design tools, process improvement tools, yield management tools and other tools essential for the continuation of Moore’s law come from the EDA industry? R & D costs are going up across the board and EDA vendors have to develop tools to satisfy different parts of the design chain. Will they be able to support the R & D investment required to develop such a broad range of tools to support the entire design to silicon shipping process without significant help from their customers? Are the foundries and IDMs going to have to start investing heavily in internal tool development? Anecdotal evidence and panel presentations suggest that the swing towards in-house tool development is continuing on an upward trend. Reference design flows, where external, commercial tools were qualified by foundries for different process technologies, worked very well for previous process nodes. But the model may be breaking down going forward because of the cost and complexity of technology involved.
  
  
  Gary Smith