Gary Smith EDA Consulting in Electronic Design

Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

  • Industry Notes are short summaries of events that will affect the electronics design world.

  • DAC 2010 – The Turn-a-Round DAC

    This year’s DAC had the right mix of Exhibits, Panels, Technical Sessions and attendees for emerging Electronic System Design (and ESL) Market. Attendance was high quality. Other topics: 3DICs, Peggy, Gadi Singer, Wallcharts and the electric cart experiment.


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    Cost: FREE


  • The First Honest FPGA Pitch

    Ok, so maybe I’m exaggerating, but Moshe’s (Xilinx) keynote at SNUG was certainly the first one I’ve seen. In the 1980s, the FPGA marketing establishment started exaggerating their capabilities. Moshe put an end to the exaggerated marketing claims because at 45nm an FPGA had enough gates to do true SoC designs.

  • Cost: FREE


  • DATE 2010: a Missed Opportunity for ESL Vendors

    DATE 2010 was a pleasant surprise and success. The venue was good; the technical conference was excellent; attendance was high quality with the continued shift to Systems and Embedded engineers and the show floor was busy. ‘Why was the show floor so poorly attended by ESL vendors?’ Poor EDA marketing

  • 4 comments

    Cost: FREE


  • 2009年亞太地區電子設計自動化會議

    2009年,在日本橫濱舉行的第十四屆亞太地區電子設計自動化會議,內容相當活潑,技術成果的發表也十分傑出。

  • Cost: FREE


  • ARM TechCon: Is Cloud Computing Just A Dream and Intel vs. ARM

    Tom Starnes had an interesting panel at ARM Techcon this year. The topic of the panel was Cloud Computing but at the end the conversation turned into a look at the competitive battle between Intel and ARM.

  • 7 comments

    Cost: FREE


  • DAC 2009 - The Congeniality DAC

    DAC is back. What was most evident was that the sense of community has returned...Social media, Sunday night, my favorite panel, Conference review.

  • 1 comments

    Cost: FREE


  • What To See @ DAC 2009 list

    The 14th annual ‘must see’ list of products includes ESL synthesis, ESL power, DRC/ Extraction, ASIC layout and Design Team E&A tools. This year we are going back to the basics. In order to receive permission to post the list on your website, you must purchase the Research Viewpoint

  • 2 comments

    Cost: FREE


  • EDP Review

    EDP again had an excellent technical program. 4 main themes: Network on Chip (NoC), RTL ASIC Hand-off, Automation of Analog Design and Parallel Computing. Gary takes an Honest Look at Parallelism with discussion of tech sessions and nVidia, Magma keynotes. EDP Presentations


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    Cost: FREE


  • IC Package and PC Board Interfaces

    Surviving another industry downturn through exploration of IC package and PC Board interfaces. Details opportunities to mitigate effects of downturn and specifically examines opportunity to optimize the Chip-Package-System co-design for competitive advantages

  • 3 comments

    Cost: FREE


  • Intel Aqcuires Wind River

    continuing the re-aggregation of the Semiconductor software stack. Discussion includes motivations and trends with embedded software companies, Intel’s interest in the Embedded Market, where Wind River fits in and Impact on Embedded SW & EDA markets.


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    Cost: FREE


  • A Simple Explanation of Multi-core

    From Von Newmann to Moore's Law to Threads and Pipe-lining to the Power Crisis to SMP & AMP. Presently we are struggling to come up with a new Compute Model of Computation so that we can develop the SW architecture and tools needed to program multi-core ICs.

  • Cost: FREE


  • What To See at DAC List

    15th annual list of 'must see' products at the 47th DAC 2010. To post / reprint the list and/or use GSEDA logo, purchase the RV for $500. View the List for Free.


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    Cost: FREE


  • EDP 2010 – A Look at the Future of IC Design

    This is a Methodologist’s Conference where presenters come in and present their ideas, not necessarily their conclusions, and then let the audience critique their approach. This makes for a rambunctious program. This year’s topics included: What Comes After CMOS and 3D-ICs.

  • Cost: FREE


  • Intel & TSMC: A Bad Deal

    This was a bad idea to begin with. The only one that had anything to gain was TSMC. By trying to mimic the ARM model, Intel would have only cannibalized their own revenue stream. Intel cannot have it both ways (IDM and Fabless.) This is not a fight to the death.


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    Cost: FREE


  • Mentor Buys Valor

    Mentor’s acquisition of Valor reflects an increasing verticalization of the PCB design to manufacturing market. PCB is one of the most mature segments of the EDA industry. Where it once accounted for the largest segment of EDA revenue, it now represents less than 10% of total EDA revenue.

  • 2 comments

    Cost: FREE


  • Hot Chips and the Future of Computing

    Something was different at Hot Chips this year, significantly different: Parallel Computing. The IC industry's shift from single processor computing to multi-core has moved us away from the Von Neumann compute model to a undefined model... endangering Moore's Law.

  • 5 comments

    Cost: FREE


  • Missing the Point

    Two acquisitions (Synfora- Esterel; Apache– Sequence) have been taken by some people as a continuation of the asset acquisitions we’ve been seeing recently.  This is a continuation of the Gloom and Doom school of thought.  Looks like some people are missing the point.

  • Cost: FREE


  • Smart Grids Bring Opportunities

    The planned investment in Smart Grids brings opportunities to EDA and Embedded Software companies. Discussion includes definition of smart grid, opportunities analysis, IT spending, and recent Standards activity.

  • Cost: FREE


  • Cadence Cuts Jobs

    The 5% layoff says that Cadence is recovering faster than expected. On the surface shutting down DFM looks like a good decision...Look a little closer however and it brings up a problem with their long term strategy

  • 1 comments

    Cost: FREE


  • ASP-DAC Review

    Japan's top conference with highlights of Toshiba and IBM keynotes, ESL methodology panel. Prescriptive Design Rules (PDR) definition and advantages vs. RDRs


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    Cost: FREE


  • DATE 2009

    Dire predictions for DATE were wrong. The technical show was excellent and my favorite part of DATE, the hallway conversations, was as active as always. Reviews Keynotes and Panels. Discusses the relationship between Marketing, Sales and Trade Shows.

  • Cost: FREE


  • Concurrent Memory - A Call to Action

    The Von Neumann compute model is the sequential single processor architecture found in most computers today. As the Power problem increased, the semiconductor vendors moved to a multi-core architecture...solving the performance problem but abandoning the Von Neumann architecture...putting into jeopardy all the companies that have made a living based on the Von Neumann compute model; Microsoft, Intel.


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    Cost: FREE


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  • 2010 Market Trends

    ESL, RTL, IC CAD, PCB market share, forecast & analysis by sub-apps
    Publish date: Oct 2010