Gary Smith EDA Consulting in Electronic Design

Gary Smith EDA (GSEDA) is the leading provider of market intelligence and advisory services for the global Electronic Design Automation (EDA), Electronic System Level (ESL) design, and related technology markets.

    Variation Analysis And Design For Custom ICs Across SOC
    Variation Analysis and Design

    One major cause of increased design costs is due to semiconductor IC scaling, as shown in Figure 1. Scaling no longer offers the “win-win” of past scaling increases which improved performance. Today, scaling increases power and variability in design. As noted in a recent worldwide custom IC survey of design engineer management, 37 percent identified variation-aware design as becoming important when designing at a 90 nanometer (nm) process node, but 60 percent saw 65nm as necessary to implement design variation and 85 percent saw it as required by 45nm.

    Figure 1 - Variation Design Tipping Point: 65nm

    Source: LaunchM Survey, 2011

    Variation design is a rapidly growing factor in custom IC design. Design variation is
    defined as the variation in parametric results caused by process and environmental (process, voltage, temperature), random variation, and layout dependent effects (parasitics, proximity). A total of 23 percent of design organizations surveyed indicated they already have variation-aware design tools deployed, and another 24 percent intend to implement those tools in 2011. A 100 percent growth in organizational adoption of variation-aware design tools is expected by year-end 2011 as custom design moves to 45nm and below process geometries. A quick look at TSMC, the largest worldwide foundry’s manufacturing capacity, indicates a ramp up in 45nm processing in Q2 of 2011. (See Figure 2).

    Figure 2 - TSMC Manufacturing Capacity, Q2 2011

    Source: TSMC, 2011

    Drivers of Variation Analysis and Design

    The top two reasons respondents gave for deploying variation-aware design systems were to improve parametric yield - performance, power and area (74%), and to avoid respins (64%). The secondary reasons noted were to avoid project delays (25%) and to save designer time (20%). A majority of engineers and managers noted that design variation has caused design and tapeout delays or respins; these factors increase engineering costs and reduce product revenue.

    Variation issues as illustrated in Figure 3, are significantly affecting design delivery. As surveyed, 53 percent of engineering management cited that their organizations had missed a project deadline, delayed a tapeout, or required a respin due to variation problems. As listed in Figure 4 in the custom IC design sectors, variation analysis and design is the custom IC focus that most needs advances within two years. 66 percent surveyed believed that variation-aware design was the area needing advances within 2 years. For those who experienced project or tapeout delays due to design variation, the average length of delay cited was 2 work-months. All told, reduced design performance, increased power and reduced parametric yield can lead to catastrophic design failure.

    Figure 3 - Types of Variation Issues

      Source: Solido Design Automation, 2011

    Figure 4 - Variation Analysis and Design

    Source: LaunchM Survey, 2011

    Foundries and Simulators

    Today multiple foundries including TSMC, GLOBAL FOUNDRIES, UMC and IDMs release models that describe variation for each manufacturing process to counter the effects of variation. This model information is then used by designers to estimate the effects of variation during the design cycle, and to improve the design making it robust to manufacturing variation effects.

    TSMC, Global Foundries and STARC have all released reference flows which incorporate variation and analysis design tools to provide design benefits discussed in this report.

    Variation analysis and design tools will be a driver for true SPICE and FastSPICE simulation at 65nm and below. Synopsys HSPICE and HSIM are the leading simulation tools for custom digital and memory designs, with Magma FineSim gaining market adoption. Cadence Spectre and APS are the leading analog simulators with Berkeley Design Automation Analog FastSPICE an emerging simulator for this market.

    SOC Trends for 65nm and below Custom IC Design

    As mentioned, variation-aware design was cited as the top segment of custom IC design where technology advancement is needed over the next 2 years. Designers named the top existing custom IC design tools they wanted to be made “variation-aware” to be layout editors, followed by true SPICE simulators, fast SPICE simulators, and then schematic capture. In that time-frame, new variation challenges are expected to emerge at smaller 28nm and below process nodes. One area of growth is expected in the area of complex SOC/SIP/POP, 3D/TSV and other IP integration strategies. Gary Smith EDA expectations for SOC growth are shown in its recent forecast in Figure 5.

    Figure 5 - Worldwide SOC Forecast

    Source: Gary Smith EDA, June 2011

    Solido Design Automation

    Founded in 2005, Solido Design Automation, Inc. is a leading privately-held start-up company providing variation analysis and design software for custom integrated circuits. Solido’s Variation Designer product is used by custom IC design teams for analog/mixed-signal, RF, I/O, memory and standard cell digital library designs to improve design performance, parametric yield, and designer productivity. Variation Designer counters process variation in custom semiconductor designs which causes yield loss and respins, which in turn can cause delays in delivering products to market, product failures and financial losses.

    Some customers started deploying Variation Designer at 130nm, but 65nm is expected to be the tipping point for implementation of variation solutions.

    Solido Variation Designer is used across the transistor-level design cycle and incorporates four platform package configurations or modules as shown in Figure 6. In a recent case study by STARC, Solido’s variation tool exceeded STARCs design performance specifications across PVT corner and local mismatch conditions. The Variation Designer solution improved total (12 hour) setup and operation times by 40 percent. The Variation Designer tool also improved MOS, resistor and capacitor area targets by up to 9 percent from the original area requirements. In other published case studies by Huawei and Qualcomm, Solido’s variation tool reduced variation design time, improved circuit performance and improved parametric yield.

    Figure 6 - Variation Designer Packages

    Source: Solido Design Automation, 2011

    TSMC and STARC have selected Variation Designer for their variation analysis and design reference flows. GLOBAL FOUNDRIES is partnering with Solido on variation analysis. Variation Designer has also been deployed for various flows such as Cadence Virtuoso Analog Design Environment (ADE) with Spectre and APS Circuit Simulators, Synopsys’ HSPICE and HSIM Circuit Simulator, Berkeley Design Automation’s Analog FastSPICE simulator, Magma FineSim simulator and Mentor Eldo simulator.

    To view entire paper, download the PDF here

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