Sept 26, 2013 1:30-2:30
Panel: Challenges System-to-Silicon Verification
We have been trying to put together an ESL design flow for over a decade. It has been very elusive. If you want excuses, the flow is complex. The RTL flow initially had only four tools, a simulator, a synthesizer, an IC Layout tool and a static timing analyzer (V-S-M-Q in LSI Logic’s terms). The other issue was that we (I specifically) were all hardware guys and half of the flow is software. It took me years to learn how to speak software so I could start to communicate with the programmers. Fortunately, I had guys like Jason Andrews (Cadence) that could translate for me when I got stuck.
Finally at DAC 2013 there were enough of us that we could start connecting the dots. I actually never got everyone in the same room together at the same time but it still got done. The next week I went back to Silicon Valley and had lunch with Frank Schirrmeister and Jason to finish off the picture. Yes, the last problem was on the software side of the flow.
So next Monday, August 19th, Frank, Jason and Mike Gianfagna (a guy who focuses on the hardware side) will get together to try to explain what happened in a webinar (register). Frank wrote a blog with some background. Now we aren’t the geniuses (certainly not me) that did the hard work; we just all knew who those geniuses were. As the old saying goes, “It’s not what you know but who you know that counts”. Therefore, I will try to thank all of the visionary people that helped to put this flow together.
I hope you can join us and have some fun.
Please come to the webinar with your questions or ask them in the comments of this blog or send me an email to [email protected]
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